Particle Swarm Optimization (PSO) is a method utilized to optimize the location of DG units in a power system. PSO involves particles moving through a search space and adjusting their positions based on their own (p_best) and nearby (g_best) particles' experiences to improve their movements continuously. A two-stage PSO methodology is utilized for optimizing the location of distributed generation units and determining the active and reactive power values (P_DG and Q_DG) at the DG bus. The improved power factor, reduced power losses and enhanced voltage stability of the system are the main objectives of this optimization process. The algorithm indirectly adjusts PDG and Q_DG values by stochastically modifying the voltage magnitude (|V_DG|) and phase (δ_DG) values in the DG block, which are considered as state variables. The objective is to optimize voltage and power factor across all buses in response to the deployment of a single DG unit.

Both PQ buses, i.e. Bus-2 and Bus-3, are equipped with 3-φ switches that connect the DGs as shown in Figure 3. For complete bus screening, only one switch needs to be turned ON to integrate a single DG at once. The network model in the loop undergoes a specified number of iterations (i) and swarms (N) to update the location (x) and velocity (v) of every swarm, and to calculate the fitness function (FF) outlined in (eqs. 1) and (2). W represents the inertia coefficient, c₁ and c₂ represents the acceleration coefficients, random numbers are represented by r₁ and r₂, p_best (g_best), represents individuals’ (global) optimum location with j showing the bus number. A restriction is imposed on the problem to ensure that |V_DG| remains below 25 kV while tuning, which aligns with the maximum voltages of the system as specified in (eqs. 3), (4), and (5):

The proposed PSO algorithm is evaluated by conducting a thorough scan of each bus and workflow of the PSO algorithm for DG placement is shown in Figure 4. This involves storing position and FF values, including switch sequences for the final evaluation of DG configurations. Following the completion of simulations, the switch sequence is applied to connect DG at different buses with FF values and positions saved after each iteration. The switch sequence for connecting DGs at Bus-2 and Bus-3 are [1 0] and [0 1] respectively. After screening all buses, the final solution is determined based on the maximum FF value, associated bus, and particle positions (|V_DG| ∠δ_DG). By continuously connecting DG to buses and scanning them separately, particles under PSO training gradually converge towards their target.

Figure 4.

Workflow of PSO algorithm for DG placement

Through an iterative switch sequence, each PQ bus is selected as the DG bus in a standard PSO implementation, allowing for the exploration of all potential combinations of particle positions. This method ensures eventual convergence towards the focal point upon completion of the entire process, although it demands substantial memory, computational resources, and time. This outcome serves as a benchmark for validating convergence precision and evaluating the effectiveness of the process. The parameters utilized in the simulation setup for optimization are detailed and quantified in Table 3, where the optimization procedures are executed.

The designed PSO algorithm successfully determined the optimal placement of a DG unit in an IEEE-3 bus system at Bus-2 with a binary sequence [1 0] for maximum output. An IEEE-3 bus system with a DG allocated at Bus-2 was utilized to obtain both powers (P_DG and Q_DG) necessary for the system. The DG bus is evaluated during optimization along with the active and reactive powers to maximize power factor and bus voltages by connecting generators at each PQ bus through switches. The identification of the most suitable bus, such as Bus-2, led to the determination of the exact values of required powers. Following the PSO implementation for optimal DG location, the active and reactive power values (P_DG and Q_DG) were obtained (see Figure 5), revealing that connecting DG at Bus-2 with |V_DG| of 25 kV and δ_DG of -31° resulted in active (P_DG) and reactive (Q_DG) power values of 3.284×10¹⁰ VA and 1.513×10¹⁰ VAR, respectively.

Figure 5.

Results for required power values for DG-bus

The next stage is to design the PV based DG system that will be installed at the DG bus after the DG position (DG bus) has been evaluated and its parameters must be adjusted for maximum throughput. The PV module is integrated with a control stage and PWM inverter subsystem to produce the three-phase reference signal for the necessary active and reactive power values. The main concept behind creating the active and reactive power pair integrating from the PV system is to create a reference signal with specific phase and amplitude, and then operate the PWM switches accordingly. The active and reactive power values required (P_DG and Q_DG) are considered as reference values (P_ref and Q_ref) for the control stage. Optimization of the grid is achieved through fine-tuning of the parameters in the DG system to regulate the flow of active and reactive powers. This includes adjusting voltage magnitude and phase, while ensuring that constraints are met during the optimization process. Next, the Photovoltaic module, Pulse Width Modulation inverter, and LCL filter are placed at the designated bus and synchronized with an advanced control system to inject the targeted active and reactive powers calculated via the PSO algorithm. Main goal of the control system is to ensure effective operation and stability by implementing phase domain control, which is facilitated by a dedicated controller shown in Figure 6.

Figure 6.

Block diagram of PV integration in IEEE-3 bus system.

The connection of PV system to a grid network is more challenging since the photovoltaic modules produce the DC output which needs to be converted into 3-φ AC. A control interface block that incorporates a control section along with the LCL filter, and PWM inverter is positioned in between IEEE-3 bus specific DG bus (Bus-2) and PV module. The presence of this interface block is important for PV systems integration into grid network and addition of the control section, LCL filter and the PWM inverter into the interface block assists in the control of flow of power and stabilizing the grid. V_PV,DC is the desired DC output of the PV module (1SOLTECH-STH-215P) used in this project with 120 parallel (N_P) and 900 series (N_S) strings [29].

P_ref and Q_ref mean the optimal active and reactive power output that is expected from the DG unit (P_DG and Q_DG) and has been calculated using PSO algorithm. These values are important for the PV system located at the DG bus regarding regulating flow of active and reactive powers in the PV module, which is both DG and grid based on the values of P_ref and Q_ref. The control of the active power (P_PV) and reactive power (Q_PV) in the PV module is done by comparing these with the reference signals (P_ref and Q_ref). This comparison is done by using two proportional-integral (PI) controllers for which the output is used as the input to the proportional-resonant (PR) controller as depicted in Figure 7. To its further power management, the PR controller then generates a voltage reference (V_ref) for the inverter input.

Figure 7.

Controller stage for tuning PPV and QPV

A 3-φ phase domain controller is designed to generate three-phase reference voltages V_{ref (a, b, c)} for a three-phase PWM inverter. The phase domain approach is used for controlling the flow of powers being injected, providing more accurate results than the DQ Mode approach but with higher complexity. Figure 8 shows a phase locked loop (PLL) block, used to determine system phase (ωt) using DG bus voltage V_DG, which is then used to calculate active and reactive currents (I_A and I_R). These current values are input to the phase domain controller, which consists of a pair of PI controllers and a single PR controller for each phase, resulting in higher design and computational costs but improved performance compared to the DQ Mode approach.

Figure 8.

Design of phase domain controller for generation of 3-φ Vref

As discussed above the controller consists of a pair of PI controllers and a PR controller for each phase. The phase domain controller has two control loops, first the active power control loop and secondly the reactive power control loop. In the active power control loop, a simple computing block is fed by the reference active power (P_ref) required to be injected in system and photovoltaic generated active power (P_PV). In the process, PV produced active power (P_PV) is compared to the reference active power (P_ref) values to obtain a controlled required value of reference current (I_ref). In reactive power control loop, a computing block is fed by the reference reactive power (Q_ref) and PV generated reactive power (Q_PV). The same process is repeated for this loop but obtained output is inverter current (I_Inv). Lastly, the I_ref and I_Inv are added by using a computing block and fed to the PR controller whose output is V_ref. The explained process is just for a single phase, and it must be done for all three phases to obtain a three phase reference voltages V_{ref (a, b, c)} as shown in Figure 8. It can be seen that overall six PI controllers; PI₁, PI₂, PI₃, PI₄, PI₅, PI₆ to regulate P_ref,a, Q_ref,a, P_ref,b, Q_ref,b, P_ref,c, and Q_ref,c, three PR controllers; PR_a, PR_b, PR_c, are used for this phase domain approach as compared to the DQ Mode approach which uses only four PI controllers and two PR controllers due to which the computational cost and time for used approach is increased but obtained results are accurate in compete with DQ Mode. Here, the control system for the present work is completed and in the next section the output of phase domain controller is fed to the 3-φ PWM inverter and designing of PWM inverter is made accordingly.

The 3-φ PV inverter is commonly structured as a closed-loop feedback control system to fulfil the static and dynamic demands of the load in the DG system. Precision in capturing the essential connection between input and output serves as the basis for examining and managing the closed-loop control system [30]. Here, the design of the three-phase PWM inverter is carried out to obtain a three-phase fundamental sinusoidal waveform output. The input to this PWM inverter is the controlled DC power generated by solar, which is the output of the phase domain controller, designed in the previous section. As shown in Figure 9, a single-phase PWM Inverter consist of four insulated gate bipolar transistor (IGBT) connected in specific pattern for switching purpose to get a sinusoidal output waveform, when dc input is provided. The four PWM signals are used here for triggering at the gate of every IGBT in an inverter design. The four switches (IGBT) are arranged in such a way that the collectors of IGBT_{1, 3} are connected via V_dc+ input and emitters of IGBT_{2, 4} are connected via V_dc- input. Next, emitters of IGBT_{1, 3} are connected to the collectors of IGBT_{2, 4} respectively. The output of single-phase inverter is taken from common point of IGBT_{3, 4} and IGBT_{1, 2} (V_a, V_aN). The same pattern is designed for all three phases of a 3-φ PWM inverter. The output of a designed 3-φ inverter is fed to a filter to get a smooth sinusoidal waveform. The filter designing is carried out in the next section.

Figure 9.

Arrangement of switches for one phase of three phase PWM inverter

The initial step in the design process of the LCL filter involves establishing simulation parameters for an IEEE 3 bus system, such as f_sw = 10 kHz, f = 60 Hz and V_base = 25 kV (∀ PQ buses). DG is required to inject the specific values of P_ref and Q_ref, these values are determined by the PSO algorithm, which represents the inverter's equivalent load, and subsequently derive the base values of resistance, inductance, and capacitance through (eqs 6), (7), (8) and (9):

The determination of DC input voltage (V_PV,DC), maximum inverter current (I_max) and voltage drop across the filter (V_f) is conducted using mathematical (eqs. 10), (11) and (12). The modulation index is denoted by M = V_ref/V_c. The values of P_ref and Q_ref obtained from the PSO algorithm may be positive or negative, reflecting on power injection or withdrawal from the system. Regardless of the direction of power flow, only the positive values are used to calculate filter parameters for logical outcomes:

The ultimate calculated values of capacitance (C_f) and inductance (L_f) of filter are determined using (eqs. 13) and (14):

The initial step in the methodology involved choosing a case for the study of the proposed method. After selecting the IEEE-3 bus system as the model for implementing the proposed technique, the results were obtained after implementing the IEEE-3 bus system in MATLAB/SIMULINK without any DG placement.

Figure 10.

Plots of voltage profile at all three buses without DG

Figure 11.

Plots of power factor (PF) at all three buses without DG

In Figure 10, the voltage profile of a network is depicted using bar graphs for V_base(yellow) and V_{No DG} (blue). V_{No DG} represents the bus voltage without any distributed generation (DG) placement, while V_base is the voltage of buses directly connected to a generator with the same voltage level across all buses. In a standard IEEE-3 bus system without DG allocation, the resultant voltage for PQ buses is lower than the respective base voltages due to power losses. Figure 11 illustrates the power factor profile of all three buses, showing PF_{No DG} (blue). Here, PF_{No DG} represents the power factor of each bus without any DG placement in the network. The value of PF at each bus in the IEEE-3 bus system is calculated by first evaluating the phase difference between the voltage and current waveform at that bus and then taking the cosine of the phase. The resultant values of voltage and power factor without any DG placement can be found in Table 4 with fitness function (FF) value of 0.7781.

When a bus (Bus-2) is selected, the parameters P_ref and Q_ref for the DG are adjusted using PSO by randomly adjusting |V_DG| and δ_DG to find the optimal values for the fitness function. The process is iterated for every bus connected to the DG, with DG location, position vectors of particle and values of fitness function saved for comparison at the end. Figure 12 displays the convergence plot of the fitness function, with the DG sequentially connected at PQ buses over 20 iterations until convergence is achieved. The fitness function incorporates normalized bus voltage and power factor values, each ranging from 0 to 1, enabling a maximum sum of 1 to be attained. The optimal fitness function value of 0.8393 is attained by connecting the DG to Bus-2 with a voltage magnitude |V_DG| of 25 kV and a phase angle (δ_DG) of -31°. This configuration results in P_ref and Q_ref values of 3.284×10¹⁰ VA and 1.513×10¹⁰ VAR, respectively. It is important to highlight that P_ref and Q_ref values indicate the total powers that need to be transferred across the DG interface placed between the Bus-2 (DG bus) and the PV module for optimal PF and bus voltage.

Figure 12.

Convergence plot of fitness function

The designing of interface of PV based system with grid network was carried in methodology including PWM inverter and LCL filter designing with their implementation in MATLAB/SIMULINK. The model specifies the calculated values of P_ref and Q_ref, as well as other parameters listed in Table 5, to maintain the flow of power from the photovoltaic bus through the network by tuning the reference signal for the pulse width modulation inverter.

Figure 13 and Figure 14 display the control response of active reactive powers (P_PV and Q_PV) regulated by PV at specified P_ref and Q_ref values. Here, red, yellow, and blue represents the three phases (a, b, c) of both the power components, which reaches the set reference values as per the control commands over a 2-second simulation period.

Figure 13.

Controller response for PPV with Pref = 3.284×1010 VA

Figure 14.

Controller response for QPV with Qref = 1.513×1010 VAR

It is evident that Q reaches the reference faster than P because its initial value is closer to the target, resulting in minimal changes during the control task. In contrast, P requires additional adjustments to meet the reference, demonstrating the system's robustness as both P and Q are inter-connected and changes in one quantity impact the other's response. The crucial aspect of the control loop is the optimization of |V_PV,AC| and δ_PV at the filter output by adjusting the phase and amplitude of V_ref in the inverter. The tuning of V_ref by all controllers for PWM inverter operation is illustrated in Figure 15, highlighting the adjustments in amplitude and phase.

Figure 15.

PWM reference tuning as a result of control action

In this section, the results of voltage and power factor profiles for three buses are analyzed but after placing a PV-based DG system at Bus-2 to inject required power and optimize the voltage and power factors for all three buses in the network.

Figure 16.

Plots of voltage profile at all three buses with PV placement as DG

Figure 17.

Plots of power factor (PF) at all three buses with PV placement as DG

Figure 16 displays the voltage profile of a network using bar graphs for V_base (yellow) and V_PVasDG (blue). V_PVasDG indicates the bus voltage after PV is placed at Bus-2 as distributed generation, while V_base represents the voltage of buses directly connected to a generator with the same voltage level. The voltage level for all PQ buses increases after PV is placed at Bus-2 as a DG, indicating improved system stability and reduced losses. Figure 17 shows the power factor profile of all three buses, with PF_PVasDG representing the power factor of each bus with PV as DG at Bus-2 in the network. The resultant values of voltage and power factor with PV placement as DG can be seen in Table 6 with fitness function (FF) value of 0.8393.

After the execution of the control program, the power factors (PF) of each of the three buses in the IEEE-3 bus network are displayed as shown in Figure 18, without distributed generation (black) and photovoltaic placement as DG (grey). Without DG, PF values are lower, particularly at Bus-1. However, on connecting DG at Bus-2 with optimized settings, power factor values increase significantly for all buses. Replacing DG at Bus-2 with PV at specified reference power values results in a simulation completion before plotting PF values at all three buses. Due to harmonic losses during the conversion from DC to AC, there are minor discrepancies in PF values but overall, the new PF values with PV integration closely align with DG placement based on PSO. Table 4 and Table 6 provide data for comparative analysis of voltage profiles and power factor at all buses.

Figure 18.

Plot of PF profile of all three buses with no DG and PV placement as DG

Figure 19 consists of bar graphs of V_base (blue), V_{No DG} (orange), and V_{PV as DG} (grey) which displays the voltage profiles of IEEE-3 bus network. Here, bus voltages for all the buses after PV placement as DG at Bus-2 are represented by V_PVasDG and bus voltage without DG placement is denoted by V_NoDG. In an ideal situation, all bus voltages should align with V_base, which is observed for the voltage-controlled bus (Bus-1) linked directly to the generator. However, due to the presence of active and reactive power losses in a standard IEEE bus network having no DG, the resultant voltages for PQ buses are below the base voltages of the system.

Figure 19.

Plot of voltage profile of all three buses with PV placement as DG and without DG

Following the assessment of DG bus and its power values, it was observed that the bus voltages significantly rose and eventually matched V_base. This trend continued even after the introduction of PV in place of DG. However, a slight discrepancy in voltage levels was noticed post PV integration, which was linked to harmonic losses presence in the PV output. This highlights the importance of careful consideration in the design of filters to address these issues.